Today complexity of chip is increased so the complexity of verification process because of time to market factor & quality of deliverable. In Entire Design Cycle from specs to silicon verification is process which takes maximum time in cycle. if we can get rid of some of verification effort then we should beat TTM factor with quality deliverable.
So the Re usability is a need of an hour to achieve this goal.
How we can resolve this issue and what exactly we re-use to achieve our goal ?
In Design cycle there are two different type of functional verification we target.Module level verification & Chip Level Verification. Almost all the peripherals inside SOC we use to verify first at module level and then we test the same peripheral inside the system. We target similar behaviour of the peripherals in both type of verification. But we use to verify same peripherals separately in both the level with same scenario & checks. we build different components to verify the same thing in different environment which takes lot of time to code components and to verify it.
During Verification process of standard protocols we use to verify design against all the Rules at pin level & block levels.Most of the protocols have Host & Device (Master or slave) blocks which communicate through the common bus for data transfer.
if you compare checker rule list of all standard protocols you will find that most of the checks are common at pin level and at block level.we need some mechanism which allow us to to re-use this common set of checks across different standard protocols and different kind of verification environment(Module & SOC).
if somehow we can reduce this gap by using same components in both type of verification & different protocols then it will save most of time of coding and we can beat TTM with Quality deliverable.
This protocol interface inspector provide library of common checks at block level,pin level & timing level which user can access from library & implement their own set of check rules by directly using or enhancing the task or function from libraries.
This Generic Protocol Interface Inspector probe to this common bus to access the data on the interface and validate against all the rules should be followed by standard protocol from Both Host & Device level by using common library developed implement protocol related checks. it will inspect transaction from host & validate it and expect some transaction from Device and validate transaction from device.
This Protocol Interface inspector will also verify the timing related rules on bus using assertion & also provide hook for enhancement to verify more rules by user.
This Protocol Interface Inspector will also verify Pin level activity on the Bus for example during certain mode of operation behaviour of pins changes & this protocol inspector validates pin level activity against all protocols pin related rules.
These Protocol Interface inspectors have Host Level & Device Level Blocks to verify all the Rules of given transaction from Host & Device.
This Protocol Interface inspector will do coverage analysis on the Bus and generate report of functionality coverage of interface. it also give report of all scenario & Errors.
This Protocol Interface will check all the rules, pin level assertions & coverage data to early verification closer.
We can use this Protocol Interface to Verify most of the standard protocols by using common library & also to verify any standards protocols Host Module, Device module at module level & Inside SOC as independent component. We need to connect all interface ports to this protocol inspector and all rules related to protocol will be verified.
so, this Generic Protocol Inspector reusable which can save lot of coding time of verification process.
